1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection transistor for a semiconductor chip and, more particularly, to an ESD protection transistor for a semiconductor chip that is tolerant of electrostatic discharges.
2. Discussion of Related Art
With the advent of the deep submicron era, semiconductor devices need to be scaled down and have a shallow junction structure. Accordingly, designers of such devices are more than ever concerned with the problem of electrostatic discharge when creating device specifications. This concern reflects that a chip must pass an ESD test range set by a user even though the device is an otherwise good chip. Therefore, recent development of semiconductor chips, has focused on making chips that have a high tolerance for ESD. For this reason, as illustrated in FIG. 1, an additional ESD protection transistor 200 is mounted on an input/output pad 100 in order to protect an internal circuit 300 from the static electricity accumulated on the pad 100.
As illustrated in FIG. 2, a conventional ESD protection transistor has a plurality of active junctions 202 formed on the semiconductor substrate (not shown). A plurality of gate electrodes 204 is arranged in parallel in the horizontal direction along the active junctions 202 on the substrate. A source (not shown) is formed in the active junction 202 on one side of the gate electrode 204. A drain (not shown) is formed in the active junction 202 on the other side of the gate electrode 204. A first conductive line 206 having a predetermined pattern is formed on the substrate. The first conductive line 206 covers the gate electrode 204 thereby integrally connecting the gate electrode 204 with the input/output pad 100 forming a first insulating layer (not shown). The first conductive line 206 is also integrally connected with the active junction along the upper part of the adjacent active junction and the drain (not shown) to thereby have a predetermined overlapping portion. A second conductive line 208 having a predetermined pattern is integrally connected with the active junction 202 along its external line and a predetermined upper portion of the source. A third conductive line 210 is formed on the first insulating layer having the first and second conductive lines 206 and 208, having the second insulating layer (not shown) therebetween, so that the source and gate electrode 204 are coupled to ground and the drain and the first conductive line 206 are commonly connected to the input/output pad 100.
The first conductive line 206 and the drain are electrically connected with each other through the first conductive plug. The first conductive plug fills in contact hole h1 of the first insulating layer. The second and third conductive lines 208 and 210 are electrically connected with each other through a second conductive plug, for example, a Tungsten (W) plug. The second conductive plug fills in contact hole h2 of the second insulating layer.
The reason for the ESD protection transistor is to protect the devices of the internal circuit from being damaged due to a sudden over-voltage supplied to the internal circuit 300 due to the static electricity accumulated in the input/output pad 100.
However, when applying the prior art ESD protection transistor 200 to the manufacture of semiconductor devices, many malfunctions caused by ESD still result. The malfunctions can be classified into two types. The first malfunction type is generated by the opening of a predetermined portion in the first conductive line 206. The second malfunction type is caused by a power leakage to the substrate because of the junction broken down by the contact spike as illustrated in FIG. 3b. The former is generated during ESD test because a high voltage is suddenly applied to the input/output pad 100 and a large amount of current flows instantaneously through the first conductive line 206 integrally connected to the pad 100, so that the conductive line 206, which is not tolerant of the high voltage, melts and breaks. The first malfunction type is illustrated as region I of FIG. 3a. To simplify the explanation, only the input/output pad 100 and the first and second conductive lines 206 and 208 are illustrated in FIG. 3a. The second malfunction type is generated during ESD test because a large amount of current is converged to the first contact and the last contact which are affected from the pad 100 and therefore the contacts, which are not tolerant of the high current, break down. The second malfunction type is illustrated as region II of FIG. 3b. In this case, only the input/output pad 100 and the first and second conductive lines 206 and 208 are shown.
The ESD malfunction types are generated because the ESD protection transistor 200 does not operate properly when a voltage is applied to all pins instantaneously. Therefore, a need exists for an ESD protection transistor that prevents semiconductor device breakdown and increases its yield.
Accordingly, the present invention is directed to an ESD protection transistor for a semiconductor chip that overcomes the problems associated with prior art ESD protection transistors.
An object of the present invention is to provide an electrostatic discharge protection transistor for a semiconductor chip by structuring the ESD protection transistor to employ a plurality of a first conductive lines directly connected with the input/output pad. By doing so, the pad and the first conductive line are integrally connected with each other at multiple points thereby preventing a malfunction due to ESD.
To achieve these and other advantages, an electrostatic discharge protection transistor for a semiconductor integrated circuit is provided. The electrostatic discharge protection transistor includes a plurality of gate electrodes formed on a semiconductor substrate having a plurality of active junctions, the plurality of gate electrodes being arranged in parallel along the active junctions. A drain region is formed on a first active junction on one side of a first gate electrode. A source region is formed in a second active junction on the other side of the first gate electrode. A first insulating layer is formed on the substrate, the first insulating layer having a plurality of contact holes that expose predetermined portions of the surface of the drain region. A first conductive line is formed on a first predetermined portion of the first insulating layer and connected to the first plurality of conductive plugs, the first conductive line being integrally connected with an input/output pad at multiple points. Finally, a second conductive line is formed on a second predetermined portion of the first insulating layer such that the first and second conductive lines do not overlap.